The vocabulary of .PDS files is given separately. The grammar and syntax for .PDS files with Boolean equations is also given separately. General comments about grammar and syntax issues follow.
Note that the first several lines of the grammar (TITLE, PATTERN, ..., DATE) are all optional. If the optional lines are omitted, warning messages will be generated. The information following these optional lines is limited to 24 characters.
The reserved word CHIP is required. The description is limited to 13 alphanumeric characters. The device name must designate a device supported by the software. The on-line databook (in PALASM2) shows which devices are supported. The names of the pins as they are used in the program follow. Traditional style dictates that the pin numbers be placed by the names using comment lines.
Some PLDs have internal global preset or reset lines which effect all the registers in the device. If the device being programmed has this feature (e.g., PAL22V10s), PALASM requires the definition of a phantom pin at the end of the pin definitions. For a 24 pin device, the phantom pin would be defined as a 25th pin. Typical names for the pin are global.rst or global.set which can then be used in the equations section, if desired. Omitting a phantom pin results in the warning "Not enough pins defined".
The STRING section is optional. It permits frequently used patterns to be replaced by a name. For example, a four-literal expression for the numeric value three could be declared as "ONE '/I3 * /I2 * I1 * I0'". Strings can contain other strings, but the references must not be recursive.
The section starting with the reserved word EQUATIONS is required. What follows is a set of Boolean equations which define the functions implemented by the PLD. The results can be combinational (designated with "="), synchronously registered (designated with ":="), or asynchronously latched (designated with "*="). The equations can span more than one line, but no single line may span more than 128 columns.
The permitted operations are the standard Boolean operators with normal precedence: NOT ("/"), AND ("*"), OR ("+"), and XOR (":+:"). Parentheses may be used to group terms.
The output can also be specified as being asserted low or asserted
high. Outputs which are to be asserted low are preceded by a slash.
For example, /Q2 = I2 + /I1 + I0 would be low when I2=1, I1=0,
and I0=1. It would be high otherwise.
The declaration section follows the same rules as for a Boolean equation design.
The type of state machine to be implemented is specified by using the reserved word MEALY_MACHINE or MOORE_MACHINE.
The global defaults provide a concise way of specifying circuit behavior for cases not explicitely defined in later parts of the design specification. Default state transitions can be specified in one of three ways:
DEFAULT_BRANCH <state name>
DEFAULT_BRANCH HOLD_STATE
DEFAULT_BRANCH NEXT_STATE
The first defaults to the specified state, the second to the same state, and the third to the next state appearing in the design description.
Default outputs can also be specified as shown below.
OUTPUT_HOLD <output pin list>
DEFAULT_OUTPUT <output pin values>
In the first case, the list specifies output pins which do not change. In the second case, the output pins go to the specified values. The character '%' preceding a pin name in a pin list denotes a "don't care" output while a '/' preceding a pin name indicates a low output value.
The optional state assignment section equates state names with a unique set of state variable values. The variable values are stored in registers. The syntax of state assignments is
<state name> = <var1val> * <var2val> * .... * <varNval>
The character '/' precedes variables which are low. State names must be unique and may contain up to 14 characters. By assigning your states values, you may get a better design than by allowing Palasm to do the assignment for you.
The state equations define the state transitions of the state machine. The syntax of each state equation is
<current state name> := <condition1> -> <next state 1>
+ <condition2> -> <next state 2>
...
+ <conditionN> -> <next state N>
+-> <local default state>
The current state and next state names are those defined in the state assignment section. The conditions are defined in the condition section. The local default state line is optional. When present, the local default state overrides any global default state definition. When absent, the global default is used. An unconditional state transition should use the reserved word VCC as the condition.
An output equation for each state equation is required if OUTPUT_HOLD (in PLS and PROSE designs) or DEFAULT_OUTPUT is specified in the design. Otherwise, the output equations are optional. If the outputs are the same as the state, do not specify output equations. Registered Mealy outputs take on new values one clock cycle after a new state is reached. All others are valid when the new state is reached. For Mealy machines, the output syntax is
<state name>.OUTF <OP> <condition1> -> <output list 1>
+ <condition2> -> <output list 2>
...
+ <conditionN> -> <output list N>
+-> <local output defaults>
For Moore machines, the syntax is
<state name>.OUTF <OP> <output list>
where <OP> is again either := for registered outputs or
= for combinational outputs. The syntax of the output list is
<pin label> * <pin label> * ... * <pin label>
where the number of labels in the list is one or more.
The condition section is used to define unique input value combinations.
These conditions are then used in the state transition section.
The condition section begins with the reserved word CONDITIONS
and is followed by a list of definitions with the following syntax:
<condition name> = <input Boolean expression>
The condition name can contain up to 14 characters and must be unique. The input Boolean expression must use input names as defined in the pin list or string section and it must be unique. Conditions involving only one input do not need to be explicitely defined. Care should be taken to define conditions so that only one is true at any given time.
The next section covers the syntax and meaning of the simulation commands as well as the interpretation of simulation results. A brief simulation command summary is also available.
COMMAND <List of pin names and values>
The list of pin names consists of the name of one or more pins, possibly qualified by the '/' character. Names are separated by blank spaces. The '/' indicates the signal is low or complemented. Its absence indicates the signal is high or uncomplemented. A '/' in the pin list will complement a '/' in the CHIP declaration section.
The PRLDF command is used to initialize the values of registers which can be loaded with a value at power-up (preloaded). For example, let P1, P2, and P3 be the output pins associated with registers which are to be preloaded with 1, 0, and 1, respectively. This would be stated in the simulation as
PRLDF P1 /P2 P3
If the device cannot be preloaded, the command simply initializes the registers. The Xeltek programmer in the EE department does not support preloading.
The SETF command specifies input signal values. For example, let I1, I2, and I3 be pins associated with input signals which are to be set to 0, 1, and 1, respectively. This would be stated in the simulation as
SETF /I1 I2 I3
The inputs will retain the values until explicitly changed. Until a value is specified, input values default to 'undefined'. SETF can be used with clock input pins.
The CLOCKF command generates a clock pulse signal on the specified clock input pins. The pulse goes low-high-low. For example, consider the clock signal CLK0. It would be pulsed by
CLOCKF CLK0
The syntax of the FOR command is
FOR <index var> := <start> TO <end> DO
BEGIN
<command list>
END
An example of the FOR command follows:
FOR J:=1 TO 8 DO
BEGIN
SETF /I0 I1
CLOCKF CLK0
END
FOR loops may be nested. The value of <start> must be less than that of <end> and both must be non-negative. If the limits are equal, the loop is NOT executed.
The syntax of the WHILE command is
WHILE <condition> DO
BEGIN
<command list>
END
An example WHILE statement:
WHILE (J <= 7) DO
BEGIN
SETF I0 I1
CLOCKF CLK1
J := J + 1
END
WHILE loops may be nested. The <condition> may be either a numeric comparison or Boolean evaluation.
The syntax of the IF...THEN...ELSE command is
IF <condition> THEN
BEGIN
<command list>
END
ELSE
BEGIN
<command list>
END
An example of an IF ... THEN ... ELSE command:
IF (/Q0 * Q1) THEN
BEGIN
SETF I0 /I1
CHECK Q1 Q2 /Q3
END
ELSE
BEGIN
SETF /I0 I3
CLOCKF CLK
CHECK /Q1 /Q2 /Q3
END
The ELSE part is optional. As with the WHILE command, the <condition> may be either a numeric comparison or Boolean evaluation
The verification commands allow the correctness of the design to be checked.
The TRACE_ON command commences the writing of specified signal values to the .TRF trace file. The syntax of the command is
TRACE_ON <list of pin names>
The signal values will be put in the file in the order they occur in the pin list and with the same polarity. The values will be recorded in the file until a TRACE_OFF command is encountered or the simulation ends. TRACE_OFF has no arguments. Different signals can be traced by specifying them in a TRACE_ON command which follows a TRACE_OFF.
The CHECK command compares simulation values with expected values. The syntax of the command is
CHECK <list of pin names and values>
The list of pin names consists of the name of one or more pins, possibly qualified by the '/' character. Names are separated by blank spaces. The '/' indicates the signal is low or complemented. Its absence indicates the signal is high or uncomplemented.
For example, suppose that at a given point in a simulation, the pins P1, P2, and P3 are to have the values 0, 1, and 0, respectively. This would be specified as
CHECK /P1 P2 /P3
As with the pin list, a '/' in the pin list will complement a
'/' in the CHIP declaration section. The following table shows
the relationship between pin declarations in the CHIP section
and pin names in the CHECK command.
| Definition in CHIP | ||
|---|---|---|
| Test Level | P1 | /P1 |
| High | P1 | /P1 |
| Low | /P1 | P1 |
| Form in CHECK Name List | ||
General flow: set registers, set input signals
oscillatory conditions
differences between expected and simulation results
Copyright © 1991, 1996 NDSU EE Dept.
Upper and lower case alphanumeric, space, tab, underscore
` ~ ! @ # $ % ^ & - { } [ ] " ? < >
Maximum of 128 characters per line
AUTHOR
BEGIN
CHECK
CHIP
CLKF
CLOCKF
CMBF
COMPANY
CONDITIONS
DATE
DEFAULT_BRANCH
DEFAULT_OUTPUT
DO
ELSE
END
EQUATIONS
FOR
GND
HOLD_STATE
IF
MASTER_RESET
MEALY_MACHINE
MOORE_MACHINE
NC
NEXT_STATE
OR
OUTPUT_ENABLE
OUTPUT_HOLD
PATTERN
POWER_UP
PRLDF
R
REVISION
RSTF
S
SETF
SIMULATION
STATE
STRING
THEN
TITLE
TRACE_OFF
TRACE_ON
TRST
VCC
WHILE
'' (Single quotes) Delimit strings , Pin list separator (comma) () Enclose pins in logic expressions ; Precede comments, which run to end of line / NOT or active-low * AND + OR :+: XOR = Combinational output *= Latched output := Registered output
/ * + :+: for NOT, AND, OR, and EXCLUSIVE OR, respectively
-> State transition (go to state ...) +-> Local default state transition (otherwise, go to state ...) % Don't care value for output (used like '/')
TITLE <Design title>
PATTERN <Identification such as file name>
REVISION <Version or other ID>
AUTHOR <Name of designer>
COMPANY <Organization name>
DATE <Relevant date>
CHIP <Description> <Device name>
; <Pin numbers, eg 1 2 3 4 5 6 7 8>
<pin names, eg Clk Clr Pre I1 I2 I3 I4 GND>
; <Pin numbers, eg 9 10 11 12 13 14 15 16>
<pin names, eg NC NC Q1 Q2 Q3 Q4 NC Vcc>
STRING <Name> '<Characters to substitute>'
<more string definitions>
EQUATIONS
<combinatorial equations of the form
OutName = Name1 Op1 Name2 .... OpN NameM>
<registered equations of the form
OutName := Name1 Op1 Name2 .... OpN NameM>
<latched equations of the form
OutName *= Name1 Op1 Name2 .... OpN NameM>
NOTE: <text> designates text which is supplied by the designer.
TITLE <Design title>
PATTERN <Identification such as file name>
REVISION <Version or other ID>
AUTHOR <Name of designer>
COMPANY <Organization name>
DATE <Relevant date>
CHIP <Description> <Device name>
; <Pin numbers, eg 1 2 3 4 5 6 7 8>
<pin names, eg Clk Clr Pre I1 I2 I3 I4 GND>
; <Pin numbers, eg 9 10 11 12 13 14 15 16 phantom>
<pin names, eg NC NC Q1 Q2 Q3 Q4 NC Vcc global>
STRING <Name> '<Characters to substitute>'
<more string definitions>
STATE
<kind of state machine>
<global defaults for when behavior is not defined
by the state equations>
<state assignment definitions>
<state transition and output definitions>
CONDITIONS
<Name> = <Boolean equations specifying condition>
NOTE: <text> designates text which is supplied by the designer.
PRLDF Initialize preloadable register outputs SETF Specify input values CLOCKF Generate clock signal for clock input
FOR...TO...DO WHILE...DO IF...THEN...ELSE
The syntax and use of these three commands is comparable to computer languages like BASIC, Modula-2, etc.
CHECK Compare expected and simulated signal values TRACE_ON Specifies signals for .TRF file and recording interval TRACE_OFF